The present invention relates to a filter circuit, and more particularly to a filter circuit which removes noise from an input signal to thereby obtain an input signal having a satisfactorily shaped waveform.
A control system for a programmable controller and the like receives a state signal indicative of the state or condition of a controlled device or system and then processes such signal to generate and output a required control signal. In this case, the state signal, i.e. an input signal of the control system, typically includes a significant amount of noise, and hence, the noise must be removed from the state signal and then the waveform of such state signal must be shaped, so as to produce the state signal with accuracy and with a timing which permits accurate processing thereof.
The present invention relates to a filter circuit for performing the above-mentioned operations. One of the examples of a conventional filter circuit is shown in FIG. 1, and the operating waveforms thereof are shown in FIGS. 2(a)-2(c). In FIG. 1, a programmable controller 10 receives a state signal 51 from an external device 9, which may be the controlled device or system. This state signal is subjected to level conversion in a circuit 11, which also provides isolation, so that the state signal 51 is converted into a signal 5, as shown in FIG. 2(a), and this signal 5 is then supplied to a capacitance-resistance (CR) filter 12. In the CR filter 12, the signal 5 is integrated by a capacitor-resistor circuit so that the noise will be removed therefrom. The CR filter 12 outputs the integrated signal as a filter output signal 15, the waveform of which is shaped by a receiver 13 having a hysteresis characteristic. As a result, as seen in FIG. 2(b) and 2(c) the shaped signal has delays 17 and 18, respectively, at the rising and falling portions thereof.
In the conventional circuit shown in FIG. 1, the following inherent problems exist. First, the "L" potential level at the input of the receiver 13 tends to be increased because of the voltage drop across the resistor in the filter circuit 12, with the undesirable possibility that the "1" signal will be misjudged as a "H" signal in the receiver 13. Also, since the charging and discharging waveforms of the capacitor are not uniform, and due to variation of the threshold value of the receiver 13, which depends on the temperature, variation of the delay times 17 and 18 are necessarily large. In addition, the hysteresis characteristic depends on the threshold voltage of the receiver input, so that it is impossible to enlarge the hysteresis width of the receiver 13. Lastly, the capacitor in the filter circuit 12 is not suitable for circuit integration.
FIG. 3 shows an example of a conventional digital filter circuit, which is disclosed in Japanese Patent Laid-Open Publication No. 61-109317; and, FIGS. 4(a)-4(e) represent a time chart showing the operation of this conventional circuit. A digital filter 1 receives a filter input signal 5, which is sampled at the D input of a shift register 30 driven by a sampling clock 7. If four successive signal samples of the filter input signal 5 are at the "H" level, so that all outputs Q.sub.1 to Q.sub.4 of the shift register 30 are at the "H" level, an output set signal 28 of level "L" is produced by a NAND gate 31, so that a flip-flop 301 is set. On the other hand, if four successive signal samples of the filter input signal 5 are at the "L" level, so that all outputs Q.sub.1 to Q.sub.4 are at the level "L", an output reset signal 29 of level "L" is produced by gate 32, so that the flip-flop 301 is reset. The output of this flip-flop 301 is taken out as a filter output signal 6.
In the conventional circuit shown in FIG. 3, if the noise 22, as shown in FIG. 4(a), is inputted before the output signal 6 is changed over, the output signal 6 may not be set until the sampling data representing the noise sample is shifted out of the shift register 30. In this case, there is a disadvantage in that the turn-on time 17 necessarily becomes large. A similar problem occurs with respect to the turn-off time 18. Hence, these delay times are undesirably affected by the noise. In addition, no consideration is given in this conventional circuit to the possibility of variable setting of the noise removal and delay time characteristic of the filter circuit, which affects the overall speed of operation of the filter circuit.
Meanwhile, Japanese Patent Laid-Open Publication No. 56-114002 discloses a filter circuit which is capable of setting a variable delay time. The noise removal characteristic and delay time can be varied in this conventional circuit by varying the capacitor storage time of a capacitor-resistor filter, and so, the foregoing disadvantages relating to the filter circuit of FIG. 1 are also present in this conventional circuit.